1. Field of Invention
The present invention relates to a chip package and a stacked structure of chip packages, and particularly to a thinned chip package and a thinned stacked structure of chip packages.
2. Description of the Related Art
In the modern information society, general users prefer electronic products having the feature of high-speed, high-quality and multifunction. In terms of product outlook, the design of electronic goes after the trend of being light, slim, short, and small. To achieve the above-mentioned object, many manufacturers introduce the concept of systematization into a circuit design to save the number of chips disposed in an electronic product. On the other hand, in terms of electronic packaging, for the design trend of being light, slim, short, and small, several package design concepts are developed, such as multi-chip module (MCM), chip scale package (CSP) and a stacked structure of chip packages.
FIG. 1 is a cross-sectional view of a conventional stacked structure of chip packages. Referring to FIG. 1, a conventional stacked structure of chip packages 100 includes a plurality of stacked chip packages 200a and 200b and a plurality of solder balls 250, wherein the chip package 200a stacked over the chip package 200b is fixed on the chip package 200b by the solder balls 250 and electrically connected to the chip package 200b via the solder balls 250. Each of the chip packages 200a and 200b includes a package carrier plate 210, a chip 220, a plurality of bumps 230, and an underfill 240. The chip 220 and the bumps 230 are disposed on the package carrier plate 210 and the chip 220 is electrically connected to the package carrier plate 210 via the bumps 230. The underfill 240 is disposed between the chip 220 and the package carrier plate 210 to encapsulate the bumps 230 and buffer the thermal stress occurring between the chip 220 and the package carrier plate 210.
The package carrier plate 210 has a plurality of conductive posts 212 and a plurality of bonding pads 214, wherein the conductive posts 212 run through the package carrier plate 210, respectively, and the bonding pads 214 are also disposed on the conductive posts 212, respectively. Besides, the solder balls 250 are further disposed between the bonding pads 214 of the chip package 200a and the bonding pads 214 of the chip package 200b, respectively. In this way, the chip packages 200a and 200b are able to electrically connect each other via the solder balls 250.
Note that the package carrier plate 210 and the chip 220 possess a certain thickness, respectively, and the bumps 230 and the solder balls 250 possess a certain height as well. Consequently, it makes the chip packages 200a and 200b keep a certain thickness, and it is hard to have the chip packages 200a and 200b thinned. Thus, for the conventional stacked structure of chip packages 100 formed by a plurality of alternately stacked chip packages (200a, 200b . . . ), the total thickness thereof would be remarkably increased, so that it cannot meet the modern design demand. In short, limited by a certain volume or thickness, it is hard to advance the package density of a conventional stacked structure of chip packages 100.